In the electronics industry, as products such as cell phones, camcorders and digital media players become smaller and smaller, increased miniaturization of integrated circuit (IC) or chip packages has become more and more critical. At the same time, higher performance and lower cost have become essential for new products.
In response to the demands for newer packaging, many innovative package designs have been conceived and brought to market. One type of package achieves smaller size through thinner package substrates upon which individual or multiple chips are mounted. In these thinner packages, a number of problems have arisen.
In particular, for technology in which flip chip interconnection is employed to interconnect the chip to the package substrate, warpage of the package substrate has become a significant limitation making it difficult to meet typical coplanarity specifications for such packages.
In a typical flip chip package, a negative, edge-downward curvature (“crying” warpage) results after chip attach and underfill processes are completed. This is expected based on the CTE (coefficient of thermal expansion) mismatch between the chip silicon and the package substrate. The resulting curvature makes it extremely difficult to meet coplanarity specifications.
In addition, the multi-chip module has achieved a prominent role in reducing the board space used by modern electronics. However, multi-chip modules, whether vertically or horizontally arranged, can also present problems because they usually must be assembled before the component chips and chip connections can be tested. That is, because the electrical bond pads on a chip are so small, it is difficult to test chips before assembly onto a substrate.
Thus, it is desirable that when chips are mounted and connected individually, the chip and connections can be tested individually, and only known-good-die (“KGD”) or chips that are free of defects are then assembled into larger circuits.
A fabrication process that uses KGD is therefore more reliable and less prone to assembly defects introduced due to bad chips. With conventional multi-chip modules, however, the chip cannot be individually identified as KGD before final assembly, leading to KGD inefficiencies and assembly process yield problems.
Another size reducing design is package level stacking or package on package (PoP) stacking. This concept includes stacking of two or more packages. KGD and assembly process yields are not an issue since each package can be tested prior to assembly, allowing KGD to be used in assembling the stack.
But package level stacking can pose other problems. One problem is package-to-package assembly process difficulties caused by irregularities in the flatness/coplanarity of the lower package. Another problem results from the desirability of making connections through stacked packages or between packages where one package may block connection of another package.
Thus, despite the advantages of recent developments in semiconductor fabrication and packaging techniques, there is a continuing need for improved packaging methods, systems, and designs for increasing semiconductor chip density in PCB assemblies.
Thus, a need still remains for an efficient 3D package stacking process. In view of the ever-increasing need to save costs and improve efficiencies, it is more and more critical that answers be found to these problems. Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.